1. Field of the Invention
The present invention relates generally to data caches, and in particular to methods and mechanisms for reducing leakage power in a system cache located in a memory controller.
2. Description of the Related Art
Integrated circuits (ICs) are often designed with the goal of minimizing power consumption. The total power consumed by an IC includes both dynamic power and leakage power. Leakage power refers to the power consumed by a device or circuit while not in use. Within an IC, a significant amount of leakage power may be lost by static random-access memory (SRAM) devices. While SRAM is a type of semiconductor memory that does not need to be refreshed like dynamic random-access memory (DRAM), SRAM is volatile since data will be lost when the SRAM is not powered. SRAM devices may include a large portion of the total area of a typical IC, and the leakage power lost by the SRAM devices may constitute a significant percentage of the overall power consumption of the IC.